eyADC-DG2 is an analog front end for the evaluation of incremental encoder with sine/cosine outputs. The chip includes two sign comparators which control an internal up-down counter. Additionally, the sine/cosine signals are converted and filtered by continuous time Delta-Sigma ADCs.
The exact angle information obtained by arctan calculation, the raw as well as filtered modulator output data can be accessed via SPI interface. Additionally, an integrated sample rate converter allows the access of the raw data when using an application clock lower then 32MHz.
An LDO, an internal reference voltage generator, and an internal clock generator provide all important functionalities for implementation of the ayADC-DG2 into application.