4 GHz Impulse-Radio Ultra-Wideband Transceiver

Fully integrated solution following IEEE802.15.6 including digital interfaces.

The eyRF-T5 is a fully integrated low-power, single chip CMOS RF transceiver IC compliant with the IEEE 802.15.8 WBAN standard and compatible with the magnetic resonance imaging (MRI). The analog front end contains receiver and transmitter circuitry which are time division duplexed to the common antenna port. The digital back end interfaces to an off-chip host processor via SPI. The transceiver can be operated in a low power mode requiring less than 10 mW at 2.5 V supply voltage (supply voltage range: 2.5 to 3.6 V).

The data bytes to be transmitted are digitally encoded into a pulse-position modulated (PPM) pulse burst with a configurable data rate from 0.487 to 15.6 Mbps. An analog switch shapes the carrier-free RF signal envelope. The VCO delivering the RF oscillation is tunable from 3.5 to 4.5 GHz with a resolution of 1.3 MHz, therefore employing all three low band UWB WBAN channels with 500 MHz bandwidth. Additionally, the pulse width may be tuned to meet the given spectral mask and the output power is configurable to meet the emission limits.
The receiving RF front end amplifies the incoming pulses in a low-noise amplifier with adjustable gain before reconstructing the signal envelope by down-converting directly to baseband. This offers a sensitivity of – 75 dBm at highest data rate. The reconstructed pulse burst exceeding a given threshold are detected and synchronized to be handed over to the digital back end where they are available to the host controller via SPI again.

The chip offers two clocking schemes: A on-chip oscillator is designed to operate at a frequency of 5 MHz using an external crystal. This frequency is used as the reference clock input of an internal PLL to generate the 62.5 MHz system clock. If the user’s system has an appropriate 62.5 MHz clock available, it may be applied to the eyRF-T5 instead of the 5 MHz reference clock bypassing the PLL.
The digital back end incorporates channel coding techniques such as a forward error correcting BCH code and an AES-128 encryption option to offer an additional level of security e.g., for sensitiv medical data. Furthermore, an 8 bit parallel SPI mode can be used to increase the data transfer between host and transmit/receive FIFO.

The development of the data communication ASIC for an electronic neuroimplant system is funded by the BMBF within the framework of the funding line Innovations in the field of innovative medical technology. Project sponsor is the company VDI/VDE Innovations + Technik GmbH.